1. Technical Field
The present invention relates generally to digital interface circuits, and more particularly, to circuits and systems that evaluate data integrity and jitter via an eye diagram or other data diagram display.
2. Description of the Related Art
Eye diagrams are commonly used to display the integrity and jitter characteristics of a data signal. Typically, eye diagrams are used to view binary data, but have also been used in analog systems to view a modulation pattern or other analog signal variation and can also be applied to digital signals having more than two levels.
In general, an eye diagram is displayed by synchronizing the data channel of an oscilloscope with the data rate of the signal under observation. The result is that the display of the data window is made stationary via the synchronization of the timebase to the data rate, thereby permitting the observation of the amount and distribution of jitter at the data window edges, as well as observing the integrity of the data within the “eye”, which is the generally empty area between the transition regions and between the two signal levels. For example, a change in data within the eye such as a spike, indicates a mechanism other than jitter that may cause data errors. At the edges of the eye, the width of the diagram gives and indication of the amount of jitter, and if gaps are seen in the transition regions, chaotic and other meta-stable phenomena can be observed as specific lines within the jitter.
Data jitter and integrity determination is necessary to evaluate the performance of high-speed interface components and interfaces, as well as other circuits where jitter affect the bit error rate (BER) and eye diagrams provide a valuable tool for such determination. Other types of signal diagrams may also be employed in synchronization with a data signal. For example, a second signal or power supply voltage may be observed for noise, crosstalk or other variation that is synchronous with the data signal used to synchronize the timebase.
In laboratory environments, high-accuracy laboratory instruments may be used to provide eye diagrams via stable reference clocks. However, the challenge of probing a very high frequency data signal and/or high-impedance data signal is significant, as the effects of the probe must be accounted for in the measurements and probe characteristics can vary over time and the probe compensation model may not be accurate under actual measurement conditions. Further, significant circuit area can be consumed in the impedance-matched and isolated output pads that permit such precision measurements. Such equipment is expensive and it is typically unfeasible to incorporate the equivalent of such instrumentation within production circuits.
On-chip sampling of a data signal is typically either performed using an internal global clock or an external sample clock with an internal delay line. Use of the internal global clock is limited in that clock jitter and data jitter cannot be separated. When an external sample clock is used, the delay accuracy, and thus the accuracy of the presumed positions of the sampled data, is difficult to control.
It is therefore desirable to provide a method and apparatus for generating a signal diagram that is low cost, can be at least partially integrated in a production circuit with no probing error.